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| www.irf.com 1 12/8/04 irlr7807zpbf irlu7807zpbf hexfet power mosfet notes through are on page 11 applications benefits very low rds(on) at 4.5v v gs ultra-low gate impedance fully characterized avalanche voltage and current high frequency synchronous buck converters for computer processor power lead-free d-pak irlr7807z i-pak irlu7807z v dss r ds(on) max qg (typ .) 30v 13.8m 7.0nc absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v i d @ t c = 100c continuous drain current, v gs @ 10v a i dm pulsed drain current p d @t c = 25c maximum power dissipation w p d @t c = 100c maximum power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds thermal resistance parameter typ. max. units r jc junction-to-case ??? 3.75 r ja junction-to-ambient (pcb mount) ??? 50 c/w r ja junction-to-ambient ??? 110 40 max. 43 30 170 20 30 0.27 20 300 (1.6mm from case) -55 to + 175
2 www.irf.com static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 30 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? 23 ??? mv/c r ds(on) static drain-to-source on-resistance ??? 11 13.8 m ? ??? 14.5 18.2 v gs(th) gate threshold voltage 1.35 1.8 2.25 v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -4.5 ??? mv/c i dss drain-to-source leakage current ??? ??? 1.0 a ??? ??? 150 i gss gate-to-source forward leakage ??? ??? 100 na gate-to-source reverse leakage ??? ??? -100 gfs forward transconductance 51 ??? ??? s q g total gate charge ??? 7.0 11 q gs1 pre-vth gate-to-source charge ??? 1.8 ??? q gs2 post-vth gate-to-source charge ??? 0.7 ??? nc q gd gate-to-drain charge ??? 2.7 ??? q godr gate charge overdrive ??? 1.8 ??? see fig. 16 q sw switch charge (q gs2 + q gd ) ??? 3.4 ??? q oss output charge ??? 4.0 ??? nc t d(on) turn-on delay time ??? 7.1 ??? t r rise time ???28??? t d(off) turn-off delay time ??? 9.8 ??? ns t f fall time ??? 3.5 ??? c iss input capacitance ??? 780 ??? c oss output capacitance ??? 180 ??? pf c rss reverse transfer capacitance ??? 100 ??? avalanche characteristics parameter units e as single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj diode characteristics parameter min. typ. max. units i s continuous source current ??? ??? 43 (body diode) a i sm pulsed source current ??? ??? 170 (body diode) v sd diode forward voltage ??? ??? 1.0 v t rr reverse recovery time ??? 23 35 ns q rr reverse recovery charge ??? 14 21 nc t on forward turn-on time v ds = v gs , i d = 250a v ds = 24v, v gs = 0v v ds = 24v, v gs = 0v, t j = 125c conditions 4.0 max. 28 12 ? = 1.0mhz i d = 12a v ds = 15v conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 15a v gs = 4.5v, i d = 12a v gs = 20v v gs = -20v v ds = 15v, i d = 12a v ds = 15v, v gs = 0v v dd = 15v, v gs = 4.5v clamped inductive load t j = 25c, i f = 12a, v dd = 15v di/dt = 100a/s t j = 25c, i s = 12a, v gs = 0v showing the integral reverse p-n junction diode. intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) mosfet symbol ??? v gs = 4.5v typ. ??? ??? i d = 12a v gs = 0v v ds = 15v www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.5v 20s pulse width tj = 175c 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 v gs , gate-to-source voltage (v) 0.1 1.0 10.0 100.0 1000.0 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) t j = 25c t j = 175c v ds = 10v 20s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 30a v gs = 10v 0.1 1 10 v ds , drain-to-source voltage (v) 0.001 0.01 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.5v 20s pulse width tj = 25c 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 10000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 4 8 12 16 q g total gate charge (nc) 0 2 4 6 8 10 12 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 24v vds= 15v i d = 12a 0.0 0.5 1.0 1.5 2.0 v sd , source-todrain voltage (v) 0.1 1.0 10.0 100.0 1000.0 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 0.1 1.0 10.0 100.0 1000.0 v ds , drain-tosource voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. threshold voltage vs. temperature 25 50 75 100 125 150 175 t c , case temperature (c) 0 10 20 30 40 50 i d , d r a i n c u r r e n t ( a ) limited by package -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 1.0 1.5 2.0 2.5 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 1.796 0.000267 1.112 0.000607 0.842 0.004249 j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 c ci= i / ri ci= i / ri 6 www.irf.com d.u.t. v d s i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13. gate charge test circuit fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 12c. maximum avalanche energy vs. drain current r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 120 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) fig 14a. switching time test circuit fig 14b. switching time waveforms v gs v ds 9 0% 10% t d(on) t d(off) t r t f v gs pulse width < 1s duty factor < 0.1% v dd v ds l d d.u.t + - www.irf.com 7 fig 15. for n-channel hexfet power mosfets ! ? " # ! ? $ ! ? "!%&!# ! ! ' (! p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop r e-applied v oltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - ? )* $$! + , ? )! (! -! . ? # $$! + / 00 ? . 1!)!. !! fig 16. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr 8 www.irf.com control fet !" # $ %& !" # #' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f ? 1 ? + q g v g f () + q oss 2 v in f ? ? ? ? " ( %& !" %& !" " ) # * % + %& !" # # , # - . / # # synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets? susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca- pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic www.irf.com 9 0 - . 12 in the assembly line "a" ass embled on ww 16, 1999 example: wi t h as s e mb l y t his is an irfr120 lot code 1234 ye ar 9 = 199 9 dat e code we e k 16 part number logo international rect ifier as s e mb l y lot code 916a irfu120 34 year 9 = 1999 dat e code or p = des ignates lead-free product (opt ional) note: "p" in assembly line position indicates "l ead-f ree" 12 34 week 16 a = as s e mb l y s i t e cod e part number irf u120 line a logo lot code as s e mb l y international rectifier 10 www.irf.com 0 - . as s e mb l y example: wit h as s e mb l y this is an irfu120 year 9 = 199 9 dat e code line a we e k 19 in t he as s e mb ly l ine "a" as s e mb le d on ww 19, 1999 lot code 5678 part number 56 irfu120 international logo rectifier lot code 919a 78 note: "p" in as s embly line pos i ti on i ndi cates " l ead- f r ee" 56 78 as s e mb l y lot code rectifier logo international irfu120 part number we e k 19 dat e code year 9 = 1999 a = assembly site code p = designates lead-free product (optional) www.irf.com 11 repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 0.39mh, r g = 25 ? , i as = 12a. pulse width 400s; duty cycle 2%. calculated continuous current based on maximum allowable junction temperature. package limitation current is 30a. when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 12/04 0 - . tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl n otes : 1 . controlling dimension : millimeter. 2 . all dimensions are shown in millimeters ( inches ). 3 . outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ |
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